NXP Semiconductors /LPC800 /CMP /CTRL

Reserved. Write as 0.

This field controls which edges on the comparator output set the COMPEDGE bit (bit 23 below): 00 = Falling edges 01 = Rising edges 1x = Both edges

0 (FALLING_EDGES): Falling edges

1 (RISING_EDGES): Rising edges

2 (BOTH_EDGES): Both edges

3 (BOTH_EDGES): Both edges

Reserved. Write as 0.

Comparator output control

0 (DIRECT): Comparator output is used directly.

1 (SYNCH): Comparator output is synchronized to the bus clock for output to other modules.

Reserved. Write as 0.

Selects positive voltage input

0 (VOLTAGE_LADDER_OUTPU): Voltage ladder output

1 (ACMP_I1): ACMP_I1

2 (ACMP_I2): ACMP_I2

3 (RESERVED): Reserved

4 (RESERVED): Reserved

5 (RESERVED): Reserved

6 (INTERNAL_REFERENCE_V): Internal reference voltage

7 (RESERVED): Reserved

Selects negative voltage input

0 (VOLTAGE_LADDER_OUTPU): voltage ladder output

1 (ACMP_I1): ACMP_I1

2 (ACMP_I2): ACMP_I2

3 (RESERVED): Reserved

4 (RESERVED): Reserved

5 (RESERVED): Reserved

6 (INTERNAL_REFERENCE_V): Internal reference voltage

7 (RESERVED): Reserved

Reserved. Write as 0.

Interrupt clear bit. To clear the COMPEDGE bit and thus negate the interrupt request, toggle the EDGECLR bit by first writing a 1 and then a 0.

Comparator status. This bit reflects the state of the comparator output.

Reserved. Write as 0.

Comparator edge-detect status.

Reserved. Write as 0.

Controls the hysteresis of the comparator. When the comparator is outputting a certain state, this is the difference between the selected signals, in the opposite direction from the state being output, that will switch the output.

0 (NONE_THE_OUTPUT_WIL): None (the output will switch as the voltages cross)

1 (5_MV): 5 mV

2 (10_MV): 10 mV

3 (20_MV): 20 mV

Reserved